1. Field of the Invention
The invention generally relates to differential pairs and, in particular, the present invention relates to a differential pair capable of attaining a high slew rate and a common mode input to ground.
2. Background of the Invention
Differential pairs are widely used in constructing analog circuits such as operational amplifiers and comparators. A conventional emitter-coupled FIG. 1a, NPN transistors 12a and 14a form the emitter-coupled differential pair driven by constant current source 10a, which provides a constant current I.sub.T, also called the tail current, to the differential pair. In FIG. 1a, a differential voltage V.sub.d represents the difference between the input voltages applied to the base terminals of transistors 12a and 14a. Collector currents I.sub.1 and I.sub.2 change in response to the differential voltage V.sub.d. However, the sum of collector currents I.sub.1 and I.sub.2 always equals I.sub.T. When transistors 12a and 14a are matched, collector currents I.sub.1 and I.sub.2 are the same and equal (1/2I.sub.T) when V.sub.d is zero, i.e., when input voltages at the base terminals of transistors 12a and 14a are the same. When a differential voltage is applied to V.sub.d, currents I.sub.1 and I.sub.2 will either increase or decrease depending on the polarity of voltage V.sub.d. Referring to FIG. 1a, if a positive V.sub.d is applied, the collector currents I.sub.1 and I.sub.2 will become: EQU I.sub.1 =1/2I.sub.T +.DELTA.I, and EQU I.sub.2 =1/2I.sub.T -.DELTA.I,
where .DELTA.I is the change in collector current due to V.sub.d. A differential output current and a differential output voltage develop at the collector terminals of transistors 12a and 14a.
A differential pair can also be constructed using MOS transistors as shown in FIG 1b. NMOS transistors 12b and 14b form a differential pair biased by current source 10b. One skilled in the art will appreciate that the operation of the MOS differential pair in FIG. 1b is analogous to the bipolar differential pair in FIG. 1a. One skilled in the art will also appreciate that PNP transistors or PMOS transistors can be used to form the differential pair as shown in FIGS. 2a and 2b respectively.
The conventional differential pairs illustrated in FIGS. 1a-b and 2a-b have several disadvantages. One disadvantage of the conventional differential pair is that in order to increase the gain of the differential pair, the tail current I.sub.T needs to be increased. In the differential pairs illustrated above, the gain is maximized when .DELTA.I, the change in collector current in response to the differential input voltage V.sub.d, is maximized. The change in current .DELTA.I is a function of the transconductance (g.sub.m) of the transistors and is defined by the equation: EQU .DELTA.I=g.sub.m V.sub.d.
The transconductance g.sub.m of a transistor is a function of the DC collector or source current and the threshold voltage of the transistor. The transconductance g.sub.m of the bipolar differential pair is given by: ##EQU1##
where V.sub.T is the threshold voltage of the bipolar transistor. Similarly, the transconductance of the MOS differential pair is given by: ##EQU2##
where K is a parameter relating to the device characteristics of the MOS transistor. In order to increase the gain of the conventional differential pair (that is, to maximize .DELTA.I), the transconductance g.sub.m of equations for g.sub.m provided above, increasing g.sub.m requires increasing the tail current I.sub.T. However, it is undesirable to increase the tail current I.sub.T because a large I.sub.T causes an increase in the quiescent current of the circuit, resulting in increased heat and power consumption.
Another disadvantage of the conventional differential pair is that the common mode input voltage V.sub.cm cannot be brought to ground while still maintaining operation of the differential pair. The common mode input voltage V.sub.cm is a voltage added to the differential input voltage V.sub.d before the input voltages are applied to the input terminals of the differential pair. Defining V.sub.1 as the input voltage applied to the gate or base of one of the transistors of the differential pair, and V.sub.2 as the input voltage applied to the base or gate of the other transistor in the differential pair, the differential input voltage V.sub.d and the common mode input voltage V.sub.cm are defined as: ##EQU3##
Following the above equations, the input voltages V.sub.1 and V.sub.2 are given by: ##EQU4##
Using the NPN differential pair of FIG. 1a as an example, voltage V.sub.cm cannot be brought to ground by setting voltages V1 and V2 to zero volt because a minimum voltage of (V.sub.BE +V.sub.CE(sat)) must be kept at the emitter terminals of transistors 12a and 14a in order to keep current source I.sub.T on. The situation is the same for the PNP differential pair shown in FIG. 2a. Since the collector terminals of transistors 22a and 22b are typically connected to a current mirror acting as an active load for the output of the differential pair. The common mode voltage V.sub.cm cannot be brought to ground because the current mirror will be shut off.
The conventional differential pair has yet another disadvantage of a limited slew rate due to the tail current I.sub.T. This is described with reference to FIG. 3, which is a circuit schematic of a conventional bipolar differential amplifier. Differential amplifier 300 includes an emitter-coupled differential pair (NPN transistors N1 and N2) coupled to a current mirror (transistors P1 and P2) as the active load. A differential voltage V.sub.d is applied to the base terminals (nodes 314 and 316) of transistors N1 and N2. Constant current source 312, connected to the emitter terminals of transistors N1 and N2 (node 308), provides a constant tail current I.sub.T to the differential pair. The output terminal of the differential pair (node 318) is connected to an integrating stage including an amplifier 302 and a compensation capacitor 304. Amplifier 302 and compensation capacitor 304 are connected in parallel between node 318 and node 320. Node 320 is the output voltage Vout of different amplifier 300.
One important performance parameter of a differential amplifier is the slew rate which measures how closely the output voltage Vout tracks changes in the input differential voltage V.sub.d. Slew rate is defined as the rate of change of the output voltage Vout before Vout reaches its final value. The slew rate is limited by the amount of current available at the output of the differential pair (node 318) to charge compensation capacitor 304 when a large differential input voltage is applied. Thus, the maximum slew rate attainable for differential amplifier 300 is limited by the maximum current that the different pair (transistors N1 and N2) can deliver at output node 318 to charge capacitor 304. For differential amplifier 300, the maximum current is the maximum collector current of transistor N2, which is the tail current I.sub.T Therefore, the maximum slew rate for differential amplifier 300 is provided by: ##EQU5##
where Cc is the capacitance of compensation capacitor 304. In order to attain a very high slew rate, either the tail current I.sub.T needs to be increased or the capacitance Cc of capacitor 304 needs to be decreased. However, it is undesirable to decrease the compensation capacitance Cc because circuit stability will be compromised. Therefore, the tail current I.sub.T has to be increased to attain a high slew rate. As described above, increasing I.sub.T is not desirable because it leads to an increase in quiescent current in the circuit.
FIG. 4 is a circuit diagram of a differential amplifier 400 constructed of an NMOS differential pair and a PMOS current mirror. One skilled in the art will appreciate that the operation of differential amplifier 400 is analogous to differential amplifier 300 in FIG. 3, and differential amplifier 400 suffers the same shortcomings as amplifier 300.
Therefore, the conventional differential pairs are unsatisfactory because gain and slew rate improvement cannot be achieved without the undesirable effect of increasing the quiescent current of the circuit. Furthermore, the common mode input voltage cannot be brought to ground while still maintaining operation of the differential pair.